CC1110-RTR1 datasheet(102/203 Pages) TI

102 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 102 of 202

13.4 MAC Timer (Timer 2)

The MAC timer is designed for slot timing

operations for MAC layers of RF protocols.

The timer includes a highly tunable

prescaler allowing the user to select a

timer tick interval that equals, or is an

integer fraction of a transmission slot.

•

8-bit timer

•

18-bit tunable prescaler

13.4.1 Timer Operation

This section describes the operation of the

timer.

The timer count can be read from the

T2CT SFR register. The timer decrements

by 1 at each timer tick. When the timer

count reaches 0x00 the timer expires and

does not wrap around. When the timer

expires, the register bit T2CTL.TEX is set

to 1. An interrupt request is generated

when the timer expires, if the interrupt

mask T2CTL.INT is 1.

When a new value is written to the timer

count register, T2CT, then this value is

stored in the counter immediately. If a tick

and a write to T2CT occurs at the same

time, the written value will be decremented

before it is stored.

The timer tick period T, is given as:

T = T2PR * Val(T2CTL.TIP) clock cycles.

where the function Val(x) is set by the tick

period, T2CTL.TIP and defined as

Val(00)=64

Val(01)=128

Val(10)=256

Val(11)=1024

The tick generator can be set to run freely

or to run only when the timer holds a non-

zero value. Whenever the tick generator is

started it starts from its zero state. At this

point there will be T2PR*Val(T2CTL.TIP)-1

clock cycles until the next tick.

13.4.2 Timer 2 Registers

The SFR registers associated with Timer 2

are listed in this section. These registers

are the following:

•

T2CTL – Timer 2 Control

•

T2PRE – Timer 2 Prescaler

•

T2CT – Timer 2 Count

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