WM8510GEDSSLASHV datasheet(66/81 Pages) WOLFSON

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WM8510

Production Data

PD Rev 4.1 December 2006

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

LOOPBACK

Digital loopback function

0=No loopback

1=Loopback enabled, ADC data output is fed directly

into DAC data input.

Digital Audio

Interfaces

CLKSEL

Controls the source of the clock for all internal

operation:

0=MCLK

1=PLL output

Digital Audio

Interfaces

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or PLL clock

output (under control of CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

Digital Audio

Interfaces

4:2

BCLKDIV

000

Configures the BCLK and FRAME output frequency,

for use when the chip is master over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Digital Audio

Interfaces

Reserved

6 (06h)

Sets the chip to be master over FRAME and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs generated by

the WM8510 (MASTER)

Digital Audio

Interfaces

8:4

00000

Reserved

3:1

000

Approximate sample rate (configures the coefficients

for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Audio Sample

Rates

7 (07h)

SLOWCLKEN

Slow clock enable. Used for both the jack insert

detect debounce circuit and the zero cross timeout.

0 = slow clock disabled

1 = slow clock enabled

Audio Sample

Rates

8:6

000

Reserved

8 (08h)

5:4

OPCLKDIV

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

General

Purpose Input

Output

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