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WM8510GEDS/V bảng dữ liệu(PDF) 60 Page - Wolfson Microelectronics plc |
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WM8510GEDS/V bảng dữ liệu(HTML) 60 Page - Wolfson Microelectronics plc |
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60 / 81 page ![]() WM8510 Production Data w PD Rev 4.1 December 2006 60 SYMBOL MIN TYPICAL MAX UNIT tline_midrail_on 500 ms tline_midrail_off 1 s thp_midrail_on 500 ms thp__midrail_off 6 s tdacint 2/fs n/fs Table 52 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time, tline_midrail_on, is mainly determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7µF capacitor. 2. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. 3. The lineout discharge time, tline_midrail_off, is dependent upon the value of the lineout coupling capacitor and the leakage resistance path to ground. The values above were measured using a 10µF output capacitor. 4. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7µF VMID decoupling capacitor. 5. The headphone discharge time, thp_midrail_off, is dependent upon the value of the headphone coupling capacitor and the leakage resistance path to ground. The values above were measured using a 100µF capacitor. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation. POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 DAC control 3 DACOSR128 0 DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) R14 ADC control 3 ADCOSR128 0 ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Table 53 ADC and DAC Oversampling Rate Selection |
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