HC705E5GRSSLASHD datasheet(90/148 Pages) NXP

90 / 148 page

Motorola Bus (M Bus) Interface

General Release Specification

MC68HC705E5 — Rev. 1.0

Motorola Bus (M Bus) Interface

11.8.3 Software Responses after Transmission or Reception of a Byte

Transmission or reception of a byte will set the data transferring bit

(MCF) to a logic 1, which indicates one byte of communication is

finished. Also, the M-bus interrupt bit (MIF) is set to generate an M-bus

interrupt if the interrupt function is enabled during initialization. Software

must clear the MIF bit in the interrupt routine first. The MCF bit will be

cleared by reading from the M-bus data I/O register (MDR) in receive

mode or writing to MDR in transmit mode. Software may serve the M-bus

I/O in the main program by monitoring the MIF bit if the interrupt function

is disabled.

The following is an example of a software response by a master

transmitter in the interrupt routine. See Figure 11-9.

ISR

BCLR

1,MSR

; CLEAR THE MIF FLAG

BRCLR

5,MCR,SLAVE

; CHECK THE MSTA FLAG,

; BRANCH IF SLAVE MODE

BRCLR

4,MCR,RECEIVE

; CHECK THE MODE FLAG,

; BRANCH IF IN RECEIVE MODE

BRSET

0,MSR,END

; CHECK ACK FROM RECEIVER

; IF NO ACK, END OF

; TRANSMISSION

TRANSMIT LDA

DATABUF

; GET THE NEXT BYTE OF DATA

STA

MDR

; TRANSMIT THE DATA

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D bảng dữ liệu(PDF) 90 Page - NXP Semiconductors

HC705E5GRS/D bảng dữ liệu(HTML) 90 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL