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HC705E5GRS/D bảng dữ liệu(PDF) 86 Page - NXP Semiconductors

tên linh kiện HC705E5GRS/D
Giải thích chi tiết về linh kiện  General Release Specification
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Motorola Bus (M Bus) Interface
General Release Specification
MC68HC705E5 — Rev. 1.0
Motorola Bus (M Bus) Interface
11.6.5 M-Bus Data I/O Register
In master transmit mode, data written to this register is sent (MSB first)
to the bus automatically. In master receive mode, reading from this
register initiates reception of the next byte of data. This is accomplished
by holding the SCL clock line low until a read of this register occurs.
Once the data is read, the device releases the SCL line to allow the
transmitting device to transmit the next byte. In slave mode, the same
function is available after it is addressed.
Address:
$001C
Bit 7
654321
Bit 0
Read:
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Write:
Reset:
Unaffected by Reset
Figure 11-8. M-Bus Data I/O Register (MDR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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