HC705E5GRSSLASHD datasheet(62/148 Pages) NXP

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Phase-Locked Loop (PLL) Synthesis

General Release Specification

MC68HC705E5 — Rev. 1.0

Phase-Locked Loop (PLL) Synthesis

Figure 9-1. PLL Circuit

To change PLL frequencies, follow the procedure outlined here:

1. Clear BCS to enable the low-frequency bus rate.

2. Clear PLLON to disable the PLL and select high bandwidth.

3. Select the speed using PS1 and PS0.

4. Set PLLON to enable the PLL.

5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and

select manual low bandwidth, wait another 10% tPLLS.

6. Set BCS to switch to the high-frequency bus rate

The user cannot switch among the high speeds with the BCS bit set.

Following the procedure above will prevent possible bursts of

high-frequency operation during the re-configuration of the PLL.

Whenever the PLL is first enabled, the wide bandwidth mode should be

used. This enables the PLL frequency to ramp up quickly. When the

output frequency is near the desired frequency, the filter is switched to

the narrow bandwidth mode to make the final frequency more stable.

LOOP FILTER

VCO

PHASE

PCOMP

PLLOUT

FREQUENCY

DIVIDER

OSC1

XFC

CRYSTAL

OSCILLATOR

PS1

PS0

TO CLOCK

DETECT

GENERATION

CIRCUITRY

CLOCK

SELECT

BCS

0.1

µF

0.1

µF

VDDSYN

tREF

tFB

÷ 2

OSC1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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