HC705E5GRSSLASHD datasheet(33/148 Pages) NXP

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MC68HC705E5 — Rev. 1.0

General Release Specification

Interrupts

General Release Specification — MC68HC705E5

Section 4. Interrupts

4.1 Contents

4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.3

Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .35

4.4

Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.5

External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.6

Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.7

Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .39

4.8

Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .40

4.9

M-Bus (I2C) Interrupt (M Bus). . . . . . . . . . . . . . . . . . . . . . . . . .40

4.10

Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.11

Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.2 Introduction

The MCU can be interrupted six different ways: the five maskable

hardware interrupts (IRQ, timer, CPI, SSI, and M bus) and the

nonmaskable software interrupt instruction (SWI).

Interrupts cause the processor to save register contents on the stack

and to set the interrupt mask (I bit) to prevent additional interrupts. The

RTI instruction causes the register contents to be recovered from the

stack and normal processing to resume.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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