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HC705E5GRS/D bảng dữ liệu(PDF) 46 Page - NXP Semiconductors |
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HC705E5GRS/D bảng dữ liệu(HTML) 46 Page - NXP Semiconductors |
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46 / 148 page ![]() Resets General Release Specification MC68HC705E5 — Rev. 1.0 Resets 5.6.4 COP Watchdog Timer Considerations If enabled by a mask option, the COP watchdog timer is active in all modes of operation (disabled in test and self-check modes). If the COP watchdog timer is selected by a mask option, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the oscillator to halt and prevent the COP watchdog timer from timing out. Therefore, it is recommended that the STOP instruction should be disabled if the COP watchdog timer is enabled. If the COP watchdog timer is selected by a mask option, the COP will reset the MCU when it times out. Therefore, it is recommended that the COP watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the COP timeout period. The recommended interactions and considerations for the COP watchdog timer, STOP instruction, and WAIT instruction are summarized in Figure 5-1. 5.7 Illegal Address Reset When an opcode fetch occurs from an address which is not implemented in the RAM ($0080–$01FF) or ROM ($0F00–$1FFF), the part is reset automatically. Table 5-1. COP Watchdog Timer Recommendations IF the Following Conditions Exist: THEN the COP Watchdog Timer Should Be: STOP Instruction Wait Time Converted to Reset WAIT Time Less Than COP Time-Out Enable or Disable COP by Mask Option Converted to Reset WAIT Time More Than COP Time-Out Disable COP by Mask Option Acts as STOP Any Length WAIT Time Disable COP by Mask Option Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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