SPC572LX datasheet(85/112 Pages) STMICROELECTRONICS

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SPC572Lx

Electrical characteristics

111

Figure 32. DSPI LVDS and CMOS master timing – output only – modified transfer

format MTFE = 1, CHPA = 1

3.17.2.2

Slave Mode timing

3. All timing values for output signals in this table are measured to 50% of the output voltage.

4. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

5. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

PCSx

SCK Output

SOUT

First Data

Data

Last Data

(CPOL = 0)

tSUO

tHO

tCSV

tSDC

tSCK

tCSH

Table 45. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)(1)

Symbol

Characteristic

Condition

Min

Max

Unit

Pad Drive

Load

1tSCK

SCK Cycle Time(2)

—

—ns

2tCSC

SS to SCK Delay(2)

—

—ns

3tASC

SCK to SS Delay(2)

—

—ns

4tSDC

SCK Duty Cycle(2)

—

—30

—

5tA

Slave Access Time(2),(3),(4)

(SS active to SOUT driven)

Very Strong

25 pF

—

Strong

50 pF

—

Medium

50 pF

—

6tDIS

Slave SOUT Disable

Time(2),(3),(4)

(SS inactive to SOUT High-Z

or invalid)

Very Strong

25 pF

Strong

50 pF

Medium

50 pF

9tSUI

Data Setup Time for Inputs(2)

—

tHI

Data Hold Time for Inputs(2)

—

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