ECE1200 datasheet(82/87 Pages) MICROCHIP

82 / 87 page

ECE1200

DS00003093C Draft-page 82

 2018-2021 Microchip Technology Inc.

9.7.12

SHALLOW PLTRST# RESET (WITHOUT POWER CYCLE)

FIGURE 9-12:

SHALLOW PLTRST# RESET (WITHOUT POWER CYCLE)

LPC_EN

(pin in)

3.3V

SUS_STAT#

(VWire Down

to pin out)

3.3V

LAD[3:0],

SERIRQ

3.3V

Running

3.3V

CLKRUN#

S0, Running

Running

SUSCLK

32KHz

3.3V

LPC_CLK[1:0]

3.3V

HOST_RESET_WARN

(VWire Down)

HOST_RESET_ACK

(VWire Up from Primary

or pin from Secondary)

Kept Running

Running

(CLKRUN bits reset)

PLTRST#

(pin in)

3.3V

Reset occurs, but there is

no edge in this case.

from PCH

Reset internally, float

Running

eSPI Bus

1.8V

Bypass

CLKRUN_CTL

bits.

No Change in Power State: LPC Bus and SERIRQ Running, and Clocks On

Driven low

Running

(LPC / SERIRQ Traffic)

Forced low

eSPI Requests done but an LPC

Mem Write may be in progress.

Wait for LPC done. No error report.

Issue Continuous Mode frame on

SERIRQ and wait for it to end.

Then send ACK rising edge.

Idle, potentially

driven

LFRAME#

3.3V

Running

Host CPU and

Main-Powered

Resources Reset, but

Main Power Rails On

Idle, driven

inactive

Initially low

(CLKRUN_CTL

bits bypassed)

S0, Reset

Continue to

Point

in Bring-Up

Diagram

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