ECE1200 datasheet(75/87 Pages) MICROCHIP

75 / 87 page

 2018-2021 Microchip Technology Inc.

DS00003093C Draft-page 75

ECE1200

9.7.5

TEARDOWN FROM S0 TO S5, LPC CLOCKS OFF

FIGURE 9-5:

TEARDOWN FROM S0 TO S5, LPC CLOCKS OFF

LPC_EN

(pin in)

3.3V

ASYNCH

Stop

SUS_STAT#

(VWire Down

to pin out)

3.3V

LAD[3:0],

SERIRQ

3.3V

Running

3.3V

CLKRUN#

as PCH_PWROK, via SLP_S3# (invisible)

Idle

Running

SUSCLK

32KHz

3.3V

LPC_CLK[1:0]

3.3V

Running

SLP_EN bit

(invisible, in PCH)

HOST_RESET_WARN

(VWire Down)

CLKRUN# high

period: stop clocks.

Idle period:

set CLKRUN# high.

S0 to Sleep

HOST_RESET_ACK

(VWire Up if CS0#,

pin out if CS1#)

Transmitted as VWire edge Up if Primary,

Presented as output pin if Secondary.

Running

(CLKRUN bits bypassed)

Running

(CLKRUN bits reset)

Idle,

float

PLTRST#

(pin in)

3.3V

Would be

reset, but no

edge in this

case.

from PCH

Reset,

float

SYNCH Restart

Sleep

S3 to S5

Running

eSPI Bus

1.8V

Bypass

CLKRUN bits.

(Host CPU reset)

Driven low

Notes in red indicate aspects unique to this scenario.

These edges happen only when a sub-S0

Sleep or Shutdown is being performed.

This response is fast because

LPC and SERIRQ are already idle.

LFRAME#

3.3V

Running

Idle

205us min

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