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ECE1200 bảng dữ liệu(PDF) 56 Page - Microchip Technology |
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ECE1200 bảng dữ liệu(HTML) 56 Page - Microchip Technology |
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56 / 87 page ![]() ECE1200 DS00003093C Draft-page 56 2018-2021 Microchip Technology Inc. 6.11.8 LPC ERROR LOG NON-POSTED REGISTER 6.11.9 LPC ERROR LOG POSTED REGISTER Index F2h of Logical Device 01h Bits Description Type Default Reset Event 7:4 Reserved R 0h - 3 IORM_CHKIDL ‘1’ = An IOCHK# event has occurred while the LPC bus is idle. ‘0’ = No IOCHK# event has occurred during LPC idle, since this bit was last cleared. R/W1C 0 eSPI_RESET 2 IORM_CHK_ACTIVE ‘1’ = An IOCHK# event has occurred during a Non-Posted transfer on LPC (I/O Read or Write, or Memory Read). ‘0’ = No IOCHK# event has occurred during a Non-Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 1 IORM_ABTSYN ‘1’ = An Abort SYNC event has occurred during a Non-Posted transfer on LPC (I/O Read or Write, or Memory Read). ‘0’ = No Abort SYNC event has occurred during a Non- Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 0 IORM_UNCL ‘1’ = An Unclaimed or Invalid SYNC event has occurred during a Non-Posted transfer on LPC (I/O Read or Write, or Memory Read). ‘0’ = No Unclaimed or Invalid SYNC event has occurred during a Non-Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET Index F3h of Logical Device 01h Bits Description Type Default Reset Event 7:3 Reserved R 00h - 2 MW_CHK_ACTIVE ‘1’ = An IOCHK# event has occurred during a Posted transfer on LPC (Memory Write). ‘0’ = No IOCHK# event has occurred during a Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 1 MW_ABTSYN ‘1’ = An Abort SYNC event has occurred during a Posted transfer on LPC (Memory Write). ‘0’ = No Abort SYNC event has occurred during a Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET 0 MW_UNCL ‘1’ = An Unclaimed or Invalid SYNC event has occurred during a Posted transfer on LPC (Memory Write). ‘0’ = No Unclaimed or Invalid SYNC event has occurred during a Posted LPC transfer, since this bit was last cleared. R/W1C 0 eSPI_RESET |
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