ECE1200 datasheet(5/87 Pages) MICROCHIP

5 / 87 page

 2018-2021 Microchip Technology Inc.

DS00003093C Draft-page 5

ECE1200

1.1

System Block Diagrams

1.1.1

GENERAL SYSTEM BLOCK DIAGRAM

The ECE1200 is shown here as a single eSPI Slave, or the Primary Slave of two or more (on eSPI_CS0#).

Note 1: SMI# can instead be presented on SER_IRQ pin (time slot 2) and propagated to the PCH as a Virtual Wire.

2: RCIN# is not supported as a PCH pin in eSPI configuration, and should be exercised internal to the PCH.

3: SUSPWRDNACK is an output extracted from a Virtual Wire, because some eSPI Chipsets do not provide

it as a physical signal. If the LPC device can use this signal for support of the “Chipset G3” Deep Power-

Down mechanism, then make the connection as shown. Otherwise, the pin may be left open.

4: SUSWARN# and SUSACK# pins provide a mandatory handshake, propagated using Virtual Wires that

may not be present as physical signals in all eSPI Chipsets. If the LPC device, or board HW, supports this

handshake for the “DSW” Deep Sleep mechanism, then it may be connected to these pins for this purpose.

Otherwise, the SUSWARN# and SUSACK# pins must be connected directly to each other at the ECE1200

as shown. Without some form of handshake connection between them, the system will not boot.

ECE1200

ESPI_RESET#

ESPI_ALERT#

ESPI_CLK

ESPI_CS#

ESPI_IO0

ESPI_IO1

ESPI_IO2

ESPI_IO3

LPC

EC or SIO

PCH

SER_IRQ

LPC_CLK0, LPC_CLK1

LFRAME#

LAD0

LAD1

LAD2

LAD3

CLKRUN#

PME# / WAKE#

SUSWARN#

LPC_EN

BOOT_DONE

SLP_S3#, SLP_S4#, SLP_S5#

SUSACK#

SCI#

SMI#

logic

SLP_SUS#

RESETI#

RSMRST#

or GPIO

SUSCLK

PLTRST#

SUS_STAT#

LPCPD#

Virtual

Wires

LRESET#

SUSPWRDNACK

VCC Power Good

(System)

PCH_PWROK

RSMRST# (typ)

(typ)

(opt)

(typ. n/c)

(opt)

DSW Logic,

if present

Chipset G3

Logic, if

present

Note 4

Note 3

Note 2

Port 92h

RCIN#

Note 1

(opt)

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