ECE1200 datasheet(19/87 Pages) MICROCHIP

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DS00003093C Draft-page 19

ECE1200

3.7

Chip Power Management Features

Various mode bits in the register set may be set in order to save power. Some of these are the standard LPC features

(Serial IRQ Quiet Mode, CLKRUN#), and some are added in order to place the part into deeper sleep states internally.

See Section 6.6, "Low Power Modes," on page 35.

Sleep states generally involve only gating clocking internally, and exiting them is nearly immediate. Waking from a Sleep

state only takes any significant amount of time if the ECE1200’s own Deep Sleep mode is selected

(VW_C10_STOPOSC in the Power Save Register) and the Host CPU is waking from the C10 power state. In this case

a delay in response happens until the 48 MHz Ring Oscillator restarts and locks again to its frequency. Note that this

delay may in turn be bypassed using the FORCE_OSC_LOCK bit, but this will provide an inaccurate (and slower) clock

until a true lock has been achieved.

A Wake from Deep Sleep may also be triggered by the CLKRUN# pin, generally because of the Quiet Mode mechanism.

It is necessary for the requesting device to tolerate the lack of LPC clocks during the Frequency Lock delay. The

ECE1200 also responds by pulling CLKRUN# low itself at this time, enabling clocks, since the interface is no longer idle.

When there is a delay involved in exiting Deep Sleep, any I/O instruction from the Host CPU will be held using the

Deferred Completion mechanism of eSPI until frequency lock has been acquired. Note that eSPI I/O traffic is not a Wake

mechanism, since the CPU has to have awakened already for it to do this. The eSPI interface will already have trans-

mitted the new HOST_C10 Virtual Wire state, which performs the Wake.

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