MCP3464T-ESLASHST datasheet(69/108 Pages) MICROCHIP

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DS20006180D-page 69

MCP3461/2/4

For continuous reading of ADCDATA in SPI Mode (0,0),

once the data have been completely read after a data

ready interrupt, the SDO pin will take the MSb value of

the previous data at the end of the reading (falling edge

of the last SCK clock). If SCK stays Idle at logic low (by

definition of Mode 0,0), the SDO pin will be updated at

the falling edge of the next data ready pulse (synchro-

nously with the IRQ pin falling edge with an output

timing of tDODR) with the new MSb of the data corre-

sponding to the data ready pulse. This mechanism

allows the device to continuously read ADC data

outputs seamlessly, even in SPI Mode (0,0).

In SPI Mode (1,1), the SDO pin stays in the last state

(LSb of previous data) after a complete reading, which

also allows seamless Continuous Read mode.

ADC output data can only be properly read after a

tDODR time, after the data ready interrupt is coming on

the IRQ pin. The tDODR timing is shorter than the time

necessary to input a command on the SDI pin, which

ensures proper reading in the case a new read com-

mand is triggered by the data ready interrupt. In case of

continuous reading (with CS pin kept logic low), the

tDODR timing must be carefully taken care of by the

MCU, but in general, the interrupt service time is longer

than the tDODR timing. Retrieving a data ready interrupt

by reading the STATUS byte or reading the IRQ

respected.

6.5

Securing Read Communications

through CRC-16 Checksum

Since some applications can generate or receive large

EMI/EMC interferences and large transient spikes, it is

helpful to secure SPI communications as much as

possible to maintain data integrity and desired

configurations during the lifetime of the application.

The communication data on the SDO pin can be

secured through the insertion of a Cyclic Redundancy

Check (CRC) checksum at the end of each read

sequence. The CRC checksum on communications

can be enabled or disabled through the EN_CRCCOM

bit in the CONFIG3 register. The CRC message

ensures the integrity of the read sequence bits

transmitted on the SDO pin.

The CRC checksum in the MCP3461/2/4 devices uses

the 16-bit CRC-16 ANSI polynomial as defined in the

IEEE 802.3 standard: x16 +x15 +x2 +1.

This polynomial can also be noted as 0x8005. CRC-16

detects all single and double-bit errors, all errors with

an odd number of bits, all burst errors of 16 bits in

length or less and most errors for longer bursts. This

allows an excellent coverage of the SPI communication

errors that can happen in the system, and heavily

reduces the risk of a miscommunication, even under

noisy environments.

When enabled, the CRC checksum (CRCCOM[15:0])

is propagated on SDO after each read communication

sequence. In case of a Static Read command, the

checksum is propagated after each register read. In

case of an Incremental Read command, the checksum

is propagated after the last register read in the register

map (address 0xF). Figure 6-12 and Figure 6-13 show

typical read communications in Static and Incremental

Read modes when the EN_CRCCOM bit is enabled.

Since the STATUS byte is propagated on SDO, it is part

of the first message, and therefore, it is included in the

calculation of the first checksum. For subsequent

checksum calculations, the message only contains the

registers that are effectively read between two

checksums.

The CRC-16 format displayed on the SDO pin depends

on the CRC_FORMAT bit in the CONFIG3 register (see

Figure 6-11). It can either be 16-bit or 32-bit format to

be compatible with both 16-bit and 32-bit MCUs. The

CRCCOM[15:0] bits calculated by the device are not

dependent on the format (the device always calculates

a 16-bit only CRC checksum).

FIGURE 6-11:

CRC Format Table for Read

Communications.

The CRC calculation computed by the device is fully

compatible with CRC hardware contained in the Direct

Memory Access (DMA) of the PIC24 and PIC32 MCU

product lines. The CRC message that should be con-

sidered in the PIC® device’s DMA is the concatenation

of the read sequence and its associated checksum.

When the DMA CRC hardware computes this extended

message, the resulted checksum should be 0x0000.

Any other result indicates that a miscommunication has

happened and that the current communication

sequence should be stopped and restarted.

CRCCOM[15:0]

0x0000

CRC_FORMAT =

0:16-bit

(Default)

CRC_FORMAT =

1:32-bit

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