MCP3464T-ESLASHST datasheet(57/108 Pages) MICROCHIP

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DS20006180D-page 57

MCP3461/2/4

5.15.3

CAUSING DELAYED

RESET/RESTART

A third group of bits will generate a Reset and restart

that induces a new start-up delay (TADC_SETUP) so that

the internal analog operating points can be settled with

the new settings before the new conversion is started.

The Reset is immediate; the start-up timer is only

restarted after a period of two MCLK periods

(necessary to handle the Reset and ensures that the

restart is synchronous with the master clock). Overall,

the delay from Reset to actual restart of the conversion

with the new settings is then two MCLK periods plus

TADC_SETUP. This group includes CONFIG0[7:6],

CLK_SEL[1:0], CS_SEL[1:0], BOOST[1:0] and the

RESERVED Address registers (0xB and 0xC). The

CS_SEL[1:0], CLK_SEL[1:0] and BOOST[1:0] bits will

induce a start-up timer delay only if they are changed

to a new value. If they are overwritten with the same

value, they will generate an immediate Reset and

restart. In SCAN mode, the Reset and restart feature

will just restart the current conversion for this group of

bits; the SCAN cycle is not modified and not restarted.

This third group of bits will induce a start-up timer

delay, even when ADC_MODE[1:0] = 10 or if the ADC

is in Standby mode.

During the Reset and restart sequence, the Reset is

immediate and resets the internal phases to the original

state, which can lead to a discontinuity in the clock out-

put frequency if the AMCLK clock output is enabled. The

restart is synchronous with the AMCLK generation and

is effective only after two MCLK periods. The restart will

also generate a conversion start pulse (only after the two

MCLK periods or the 2 MCLK + TADC_SETUP necessary

for the restart) if enabled for the user to be able to align

the system with the exact start of the new conversion.

In MUX mode, the TIMER and SCAN registers do not

generate a Reset and restart when written, except if the

SCAN register is modified to effectively enter in SCAN

mode. In this case, the MUX mode is superseded by

the SCAN mode immediately.

In SCAN mode, a write access of the SCAN register,

during or between conversions within the SCAN cycle,

will create a Reset and restart of the whole SCAN

sequence. Within the same conditions, a write access

on the TIMER register will not create a Reset and

restart of the whole SCAN sequence. However, during

the TTIMER_SCAN delay between each SCAN cycle, a

write on the SCAN register will not generate a Reset

and restart of the whole sequence. Within the same

conditions, a write on the TIMER register will generate

a Reset and restart of the whole sequence.

Depending on the phase between AMCLK and the SPI

commands, the two MCLK period delay can become a

four MCLK delay to ensure the proper synchronization

of the device. If very precise synchronization is

required, it is recommended to either not change

dynamically the register configurations (i.e., not during

conversions), or to use the EN_STP = 1 setting so that

the start of the conversions can be clearly determined.

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