MCP3464T-ESLASHST datasheet(25/108 Pages) MICROCHIP

25 / 108 page

 2019-2021 Microchip Technology Inc.

DS20006180D-page 25

MCP3461/2/4

3.3.4

SERIAL DATA INPUT PIN (SDI)

This is the SPI data input pin and it uses Schmitt

Trigger structure. When CS is logic low, this pin is used

to send a COMMAND byte just after the CS falling

edge, which can be followed by data words of various

lengths. Data are clocked into the device on the rising

edge of SCK. Toggling SDI while reading a register has

no effect.

3.4

IRQ/MDAT

This is the digital output pin. This pin can be configured

for Interrupt (IRQ) or Modulator Data (MDAT) output

using

the

IRQ_MODE[1]

bit

setting.

When

IRQ_MODE[1] = 0 (default), this pin can output all four

possible interrupts (see Section 6.8 “Interrupts

Description”). The inactive state of the pin is

selectable through the IRQ_MODE[0] bit setting

(high-Z or logic high).

When IRQ_MODE[1] = 1, this pin outputs the modula-

tor output synchronously with AMCLK (that can be

selected as an output on the MCLK pin). In this mode,

the POR and CRC interrupts can still be generated as

they are high-level interrupts and will lock the

IRQ/MDAT pin to logic low until they are cleared.

When the IRQ pin is in High-Z mode, an external

pull-up resistor must be connected between DVDD and

the IRQ pin. The device needs to be able to detect a

Logic High state when no interrupt occurs in order to

function properly (the pad has a Schmitt Trigger input

to detect the state of the IRQ pin just like the user is

seeing it). The pull-up value can be equal to

100-200 k

 for a weak pull-up using the typical clock

frequency. The pull-up resistor value needs to be

chosen in relation with the load capacitance of the IRQ

output, the MCLK frequency and the DVDD supply

voltage, so that all interrupts can be detected correctly

by the SPI host device.

3.5

MCLK

This pin is either the MCLK digital input pin for the ADC

or the AMCLK digital output pin, depending on the

CLK_SEL[1:0] bits setting in the CONFIG0 register.

The typical clock frequency specified is 4.9152 MHz. To

optimize the ADC for accuracy and ensure proper oper-

ation, AMCLK should be limited to a certain range

depending on BOOST and GAIN settings. The higher

GAIN settings require higher BOOST settings to

maintain high bandwidth, as the input sampling

capacitors have a larger value. Figure 2-20 to

Figure 2-24 represent the typical accuracy (SINAD)

expected with the different combinations of BOOST

and GAIN settings, and can be used to determine an

optimal set for the application depending on the

sampling speed (AMCLK) chosen. MCLK can take

larger values as long as the prescaler settings

(PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the

defined range in typical performance curves.

3.6

Digital Ground (DGND)

DGND is the ground connection to internal digital

circuitry. To ensure accuracy and noise cancellation,

DGND must be connected to the same ground as AGND,

preferably with a star connection. If a digital ground

plane is available, it is recommended for this pin to be

tied to this plane of the PCB. This plane should also

reference all other digital circuitry in the system. DGND

is not connected internally to AGND and must be

connected externally.

3.7

Digital Power Supply (DVDD)

DVDD is the power supply pin for the digital circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended

connect

appropriate

bypass

capacitors (typically a 10 µF ceramic in parallel with a

0.1 µF ceramic). DVDD is monitored by the DVDD POR

monitoring circuit for the digital section.

3.8

Analog Power Supply (AVDD)

AVDD is the power supply pin for the analog circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended

connect

appropriate

bypass

capacitors (typically a 10 µF ceramic in parallel with a

0.1 µF ceramic). AVDD is monitored by the AVDD POR

monitoring circuit for the analog section.

3.9

Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry. To ensure accuracy and noise cancellation,

this pin must be connected to the same ground as

DGND, preferably with a star connection. If an analog

ground plane is available, it is recommended that this

pin be tied to this plane of the PCB. This plane should

also reference all other analog circuitry in the system.

AGND is the biasing voltage for the substrate of the die

and is not connected internally to DGND.

3.10

Exposed Pad (EP)

This pad is internally connected to AGND. It must be

connected to the analog ground of the PCB for optimal

accuracy and thermal performance. This pad can also

be left floating if necessary.

MCP3464T-E/ST bảng dữ liệu(PDF) 25 Page - Microchip Technology

MCP3464T-E/ST bảng dữ liệu(HTML) 25 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL