MCP3464T-ESLASHST datasheet(35/108 Pages) MICROCHIP

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DS20006180D-page 35

MCP3461/2/4

5.2

Input Impedance

The ADC inputs (VIN-/VIN+) are directly tied to the

analog multiplexer outputs and are not routed to

external pins. The multiplexer input stage contribution

to the input impedance is negligible.

The conversion accuracy can be affected by the input

signal source impedance when any external circuit is

connected to the input pins. The source impedance

adds to the internal impedance and directly affects the

time required to charge the internal sampling capacitor.

Therefore, a large input source impedance connected

to the input pins can increase the system performance

errors, such as offset, gain and Integral Nonlinearity

(INL). Ideally, the input source impedance should be

near zero. This can be achievable by using an opera-

tional amplifier with a closed-loop output impedance of

tens of ohms.

A proper anti-aliasing filter must be placed at the ADC

inputs. This will attenuate the frequency contents

around DMCLK and keep the desired accuracy over

the baseband (DRCLK) of the converter.

This anti-aliasing filter can be a simple first-order RC

network with low time constant that will provide a high

rejection at DMCLK frequency (see Figure 5.6 for more

details). The RC network usually uses small R and

large C to avoid additional offset due to IR drop in the

signal path. This anti-aliasing filter will induce a small

systematic gain error on the AC input signals that can

be compensated in the digital section with the Digital

Gain Error Calibration register (GAINCAL).

5.3

ADC Programmable Gain

The gain of the converter is programmable and

controlled by the GAIN[2:0] bits in the CONFIG2

gain stages: one in the analog domain, one in the digital

domain as per Table 5-3.

After the multiplexer, the analog input signals are

routed to the Delta-Sigma ADC inputs and are

amplified by the analog gain stage (see Section 5.3.1

“Analog Gain” for more details). The digital gain stage

is placed inside the digital decimation filter (see

Section 5.3.2 “Digital Gain” for more details).

5.3.1

ANALOG GAIN

The gain settings, from 0.33x to 16x, are done in the

analog domain. This analog gain is placed on each

ADC differential input. Each doubling of the gain

improves the thermal noise due to sampling by

approximately 3 dB, which means the lowest noise

configuration is obtained when using the highest analog

gain. The SNR, however, is degraded since doubling the

gain factor reduces the maximum allowable input signal

amplitude by approximately 6 dB.

If the gain is set to 0.33x, the differential input range

becomes theoretically ±3 * VREF; however, the device

does not support input voltages outside of the power

supply voltage range. If large reference voltages are

used with this gain, the input voltage range will be

clipped between AGND and AVDD, and therefore, the

output code span will be limited. This gain is useful

when the reference voltage is small and when the input

signal voltage is large.

The analog gain stage can be used to amplify very low

signals, but the differential input range of the

Delta-Sigma modulator must not be exceeded.

TABLE 5-3:

SIGMA-DELTA ADC GAIN SETTINGS

GAIN[2:0]

Total Gain

(V/V)

Analog Gain

(V/V)

Digital Gain

(V/V)

Total Gain

(dB)

VIN Range (V)

0.333

-9.5

±Min (AVDD,

3*VREF)

±VREF

±VREF/2

±VREF/4

±VREF/8

±VREF/16

±VREF/32

±VREF/64

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