STM32H723VG datasheet(195/227 Pages) STMICROELECTRONICS

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DS13313 Rev 2

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STM32H723xE/G

Electrical characteristics

208

I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 108 for I2S are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 12: General operating conditions, with the following

configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load CL = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CK,SD,WS).

Table 108. I2S dynamic characteristics(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

I2S main clock output

MHz

Master transmitter

50/40(2)

2. This value is obtained when PA9 or PA12 are used.

Master receiver

50/40(2)

Slave transmitter

41.5/31(3)

3. This value is obtained when PC2 is used.

Slave receiver

tv(WS)

WS valid time

Master mode

-2/6(4)

4. This value is obtained when PA11 or PA15 are used.

th(WS)

WS hold time

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

tsu(SD_MR)

Data input setup time

Master receiver

2.5

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

1.5

tv(SD_ST)

Data output valid time

Slave transmitter (after enable

edge)

12/16(3)

tv(SD_MT)

Master transmitter (after

enable edge)

-2/6(5)

th(SD_ST)

Data output hold time

Slave transmitter (after enable

edge)

6.5

th(SD_MT)

Master transmitter (after

enable edge)

0.5

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