STM32H723VG datasheet(170/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

170/227

DS13313 Rev 2

6.3.23

DAC characteristics

1. Guaranteed by characterization for BGA packages. The maximum values are preliminary data. The values for LQFP

packages may be different.

2. ADC DC accuracy values are measured after internal calibration in Continuous and Discontinuous mode.

3. TBD stands for “to be defined”.

Table 85. DAC characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Analog supply voltage

1.8

3.3

3.6

VREF+

Positive reference voltage

1.80

VDDA

VREF-

Negative reference

voltage

VSSA

Resistive Load

DAC output buffer

connected

to VSSA

kΩ

connected

to VDDA

Output Impedance

DAC output buffer OFF

10.3

RBON

Output impedance

sample and hold mode,

output buffer ON

DAC output buffer

VDD = 2.7 V

1.6

kΩ

VDD = 2.0 V

2.6

RBOFF

Output impedance

sample and hold mode,

output buffer OFF

DAC output buffer

OFF

VDD = 2.7 V

17.8

kΩ

VDD = 2.0 V

18.7

Capacitive Load

DAC output buffer OFF

CSH

Sample and Hold mode

0.1

µF

VDAC_OUT

Voltage on DAC_OUT

output

DAC output buffer ON

0.2

VDDA

−0.2

DAC output buffer OFF

VREF+

tSETTLING

Settling time (full scale:

for a 12-bit code transition

between the lowest and

the highest input codes

when DAC_OUT reaches

the final value of ±0.5LSB,

±1LSB, ±2LSB, ±4LSB,

±8LSB)

Normal mode, DAC

output buffer ON,

CL ≤ 50 pF,

RL ≥ 5 ㏀

±0.5 LSB

2.05

µs

±1 LSB

1.97

2.87

±2 LSB

1.67

2.84

±4 LSB

1.66

2.78

±8 LSB

1.65

2.7

Normal mode, DAC output buffer

OFF, ±1LSB CL=10 pF

-1.7

tWAKEUP(2)

Wakeup time from off

state (setting the ENx bit

in the DAC Control

value of ±1LSB is reached

Normal mode, DAC output buffer

ON, CL ≤ 50 pF, RL = 5 ㏀

-5

7.5

µs

Normal mode, DAC output buffer

OFF, CL ≤ 10 pF

PSRR

DC VDDA supply rejection

ratio

Normal mode, DAC output buffer

ON, CL ≤ 50 pF, RL = 5 ㏀

−80

−28

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