TAS5822MDCPR datasheet(23/90 Pages) TI

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capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the

power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the

gate-drive regulator output pin (AVDD) and the bootstrap pin. When the power-stage output is high, the

bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for

the high-side gate driver.

7.3.2 Device Clocking

The TAS5822M devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio

Interface.

Serial Audio

Interface (Input)

DSP

(Including

interpolator)

Delta Sigma

Modulator

DAC

Audio In

LRCLK/FS

DSPCLK

OSRCLK

DACCLK

Figure 7-1. Audio Flow with Respective Clocks

Figure 7-1 shows the basic data flow and clock Distribution.

The Serial Audio Interface typically has 3 connection pins which are listed as follows:

• SCLK (Bit Clock)

• LRCLK/FS (Left Right Word Clock and Frame Sync)

• SDIN (Input Data)

The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP

and the DAC clock.

The device has an audio sampling rate detection circuit that automatically senses which frequency the sampling

rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz are

supported. The sampling frequency detector sets the clock for DAC and DSP automatically.

7.3.3 Serial Audio Port – Clock Rates

The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK and SDIN. SCLK is the

serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio

interface. Serial data is clocked into the TAS5822M device on the rising edge of SCLK. The LRCK/FS pin is the

serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

Table 7-1. Audio Data Formats, Bit Depths and Clock Rates

FORMAT

DATA BITS

MAXIMUM LRCLK/FS FREQUENCY

(kHz)

SCLK RATE (fS)

I2S/LJ/RJ

32, 24, 20, 16

32 to 96

64, 32

TDM

32, 24, 20, 16

128

44.1,48

128,256,512

128,256

Before DSP register initialize with I 2C during the startup , requires stable I 2S ready. When Clock halt, non-

supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register 113 (Register

Address 0x71).

7.3.4 Clock Halt Auto-recovery

As some of host processor will Halt the I2S clock when there is no audio playing. When Clock halt, the device

puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio

clocks recovery, the device automatically returns to the previous state.

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TAS5822M

SLASEV8 – DECEMBER 2020

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