TAS5822MDCPR datasheet(36/90 Pages) TI

36 / 90 page

registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book

0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register

location where it is read.

7.5.3 Control via Software

• Startup Procedures

• Shutdown Procedures

7.5.3.1 Startup Procedures

1. Configure ADR/ FAULT pin with proper setting for I2C device address.

2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).

3. Once all power supplies are stable, bring up the PDN HIGH.

4. Once I2S clock are stable, configure the device via the I2C control port based on the user cases (Make sure

the PDN pin = HIGH before I2C control port operating).

5. The device is now in normal operation.

Figure 7-15. Startup sequence

Deep sleep

DSP Coeff

Play

Initialization

Normal Operation

5 ms for device settle down

Set to Hi-Z state

(Enable DSP)

No sequence requirement

PVDD stable

DVDD stable

DVDD

PVDD

PDN

No sequence requirement

7.5.3.2 Shutdown Procedures

1. The device is in normal operation.

2. Configure the Register 0x03h -D[1:0]=00 (DEEP SLEEP) via the I2C control port or Pull PDN low.

3. The clocks can now be stopped and the power supplies brought down.

4. The device is now fully shutdown and powered off.

Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I

2C.

At least 6ms delay needed based on LRCLK (Fs) = 48kHz,Digital volume ramp down update every sample period,

decreased by 0.5dB for each update, digital volume =24dB. Change the value of register 0x4C and 0x4E or change

the LRCLK rate, the delay changes.

6ms

0ms

PDN

PVDD

DVDD

4.5V

Output Hiz

6ms

Figure 7-16. Power down sequence

TAS5822M

SLASEV8 – DECEMBER 2020

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