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TAS5822MDCPR bảng dữ liệu(PDF) 44 Page - Texas Instruments |
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TAS5822MDCPR bảng dữ liệu(HTML) 44 Page - Texas Instruments |
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44 / 90 page ![]() 7.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00] CLOCK_DET_CTRL is shown in Figure 7-18 and described in Table 7-14. Return to Table 7-7. Figure 7-18. CLOCK_DET_CTRL Register 7 6 5 4 3 2 1 0 RESERVED DIS_DET_PLL DIS_DET_BCL K_RANGE DIS_DET_FS DIS_DET_BCL K DIS_DET_MISS RESERVED DIS_DET_LOC K R/W R/W R/W R/W R/W R/W R/W R/W Table 7-14. CLOCK_DET_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0 This bit is reserved 6 DIS_DET_PLL R/W 0 Ignore PLL overate Detection This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error will be reported. When ignored, a PLL overrate error will not cause a clock error. 0: Regard PLL overrate detection 1: Ignore PLL overrate detection 5 DIS_DET_BCLK_RANGE R/W 0 Ignore BCK Range Detection This bit controls whether to ignore the BCK range detection. The BCK must be stable between 256KHz and 50MHz or an error will be reported. When ignored, a BCK range error will not cause a clock error. 0: Regard BCK Range detection 1: Ignore BCK Range detection 4 DIS_DET_FS R/W 0 Ignore FS Error Detection This bit controls whether to ignore the FS Error detection. When ignored, FS error will not cause a clock error.But CLKDET_STATUS will report fs error. 0: Regard FS detection 1: Ignore FS detection 3 DIS_DET_BCLK R/W 0 Ignore BCK Detection This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 512FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error. 0: Regard BCK detection 1: Ignore BCK detection 2 DIS_DET_MISS R/W 0 Ignore BCK Missing Detection This bit controls whether to ignore the BCK missing detection. When ignored an BCK missing will not cause a clock error. 0: Regard BCK missing detection 1: Ignore BCK missing detection 1 RESERVED R/W 0 This bit is reserved 0 DIS_DET_LOCK R/W 0 This bit is reserved 7.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h] SDOUT_SEL is shown in Figure 7-19 and described in Table 7-15. Return to Table 7-7. Figure 7-19. SDOUT_SEL Register 7 6 5 4 3 2 1 0 RESERVED SDOUT_SEL R/W TAS5822M SLASEV8 – DECEMBER 2020 www.ti.com 44 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TAS5822M |
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