TAS5822MDCPR datasheet(58/90 Pages) TI

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7.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]

ADR_PIN_CONFIG is shown in Figure 7-38 and described in Table 7-34.

Return to Table 7-7.

Figure 7-38. ADR_PIN_CONFIG Register

RESERVED

ADR_PIN_CONFIG

R/W

Table 7-34. ADR_PIN_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

RESERVED

R/W

000

This bit is reserved

4-0

ADR_PIN_CONFIG

R/W

00000

00000: off (low)

00011: Auto mute flag (asserted when both L and R channels are

auto muted)

00100: Auto mute flag for left channel

00101: Auto mute flag for right channel

00110: Clock invalid flag (clock error or clock missing)

00111: Reserved

01000: Reserved

01001: Reserved

01011: ADR as FAULTZ output

7.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]

DSP_MISC is shown in Figure 7-39 and described in Table 7-35.

Return to Table 7-7.

Figure 7-39. DSP_MISC Register

BYPASS_CONTROL

R/W

Table 7-35. DSP_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

BYPASS CONTROL

R/W

0000

These bits are reserved

1: Left and Right will have use unique coef

0: Right channel will share left channel coefficient

This bit is reserved

1: Bypass DRC

1: Bypass EQ

7.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]

DIE_ID is shown in Figure 7-40 and described in Table 7-36.

Return to Table 7-7.

Figure 7-40. DIE_ID Register

DIE_ID

R-0h

TAS5822M

SLASEV8 – DECEMBER 2020

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