TAS5822MDCPR datasheet(33/90 Pages) TI

33 / 90 page

Note

1) With Hybrid Modulation, users need to input the system's PVDD value via device development App.

2) With Hybrid Modulation, Change device state from Deep Sleep Mode to Play Mode, specific

sequence is required:

1. Set device's PWM Modulation to BD or 1SPW mode via Register (Book0/Page0/Register0x02h, Bit

[1:0]).

2. Set device to Hi-Z state via Register (Book0/Page0/Register0x03h, Bit [1:0]).

3. Delay 2ms.

4. Set device's PWM Modulation to Hybrid mode via Register (Book0/Page0/Register0x02h, Bit [1:0]).

5. Delay 15ms.

6. Set device to Play state via Register (Book0/Page0/Register0x03h, Bit [1:0]).

7.5 Programming and Control

7.5.1 I2 C Serial Communication Bus

The device has a bidirectional serial control interface that is compatible with the Inter IC ( I2)C bus protocol and

supports 100 and 400-kHz data transfer rates for random and sequential write and read operations as a slave

device. Because the TAS5822M register map and DSP memory spans multi pages, the user should change from

page to page before writing individual register or DSP memory. Changing from page to page is accomplished via

7.5.2 Slave Address

The TAS5822M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are

factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be user-

defined by ADR/ FAULT pin in Table 7-6.

Table 7-6. I2 C Slave Address Configuration

ADR/ FAULT PIN

Configuration

MSBs

User Define

LSB

4.7k Ω to DVDD

R/ W

15kΩ to DVDD

R/ W

47kΩ to DVDD

R/ W

120kΩ to DVDD

R/ W

7.5.2.1 Random Write

As shown in Figure 7-11, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address

and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte

corresponding to the internal memory address being accessed. After receiving the address byte, the device

again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the

memory address being accessed. After receiving the data byte, the device again responds with an acknowledge

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Acknowledge

Start

Condition

2C Device Address

and R/W Bit

Subaddress

Data Byte

Stop

Condition

ACK

A0 ACK

A0 R/W ACK A7

Figure 7-11. Random Write Transfer

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TAS5822M

SLASEV8 – DECEMBER 2020

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