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TAS5822MDCPR bảng dữ liệu(PDF) 46 Page - Texas Instruments

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TAS5822MDCPR bảng dữ liệu(HTML) 46 Page - Texas Instruments

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7.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in Figure 7-20 and described in Table 7-16.
Return to Table 7-7.
Figure 7-20. I2S_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
BCK_INV
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R
R
R/W
Table 7-16. I2S_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5
BCK_INV
R/W
0
BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the rising
edge of the BCK. Normally they are assumed to be aligned to the
falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode
4-0
RESERVED
R/W
00000
This bit is reserved
TAS5822M
SLASEV8 – DECEMBER 2020
www.ti.com
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