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TAS5822MDCPR bảng dữ liệu(PDF) 63 Page - Texas Instruments

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TAS5822MDCPR bảng dữ liệu(HTML) 63 Page - Texas Instruments

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7.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
SS_CTRL0 is shown in Figure 7-44 and described in Table 7-40.
Return to Table 7-7.
Figure 7-44. SS_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SS_PRE_DIV_
SEL
SS_MANUAL_
MODE
RESERVED
SS_RDM_EN
SS_TRI_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 7-40. SS_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6
RESERVED
R/W
0
This bit is reserved
5
SS_PRE_DIV_SEL
R/W
0
Select pll clock divide 2 as source clock in manual mode
4
SS_MANUAL_MODE
R/W
0
Set ramp ss controller to manual mode
3-2
RESERVED
R/W
0
This bit is reserved
1
SS_RDM_EN
R/W
0
Random SS enable
0
SS_TRI_EN
R/W
0
Triangle SS enable
7.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in Figure 7-45 and described in Table 7-41.
Return to Table 7-7.
Figure 7-45. SS_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
SS_RDM_CTRL
SS_TRI_CTRL
R/W
R/W
R/W
Table 7-41. SS_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-4
SS_RDM_CTRL
R/W
000
Random SS range control
3-0
SS_TRI_CTRL
R/W
0000
Triangle SS frequency and range control
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TAS5822M
SLASEV8 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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