PIC16F913 datasheet(90/272 Pages) MICROCHIP

90 / 272 page

PIC16F917/916/914/913

DS41250E-page 88

Preliminary

6.5

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during Sleep and can

generate an interrupt-on-overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 6.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L, while the timer is running

from an external asynchronous clock, will ensure a

valid read (taken care of in hardware). However, the

user should keep in mind that reading the 16-bit timer

in two 8-bit values itself, poses certain problems, since

the timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the timer register.

Reading

the

16-bit

value

requires

some

care.

Examples in the “PICmicro® Mid-Range MCU Family

Reference Manual” (DS33023) show how to read and

write Timer1 when it is running in Asynchronous mode.

6.6

TIMER1 OSCILLATOR

To minimize the multiplexing of peripherals on the I/O

ports, the dedicated TMR1 oscillator, which is normally

used for TMR1 real-time clock applications, is eliminated.

Instead, the TMR1 module can enable the LP oscillator.

If the microcontroller is programmed to run from

INTOSC with no CLKO or LP oscillator:

Setting the T1OSCEN and TMR1CS bits to ‘1’

will enable the LP oscillator to clock TMR1 while

the microcontroller is clocked from either the

INTOSC or LP oscillator. Note that the T1OSC

and LP oscillators share the same circuitry.

Therefore, when LP oscillator is selected and

T1OSC is enabled, both the microcontroller and

the Timer1 module share the same clock

source.

Sleep mode does not shut off the LP oscillator

operation (i.e., if the INTOSC oscillator runs the

microcontroller, and T1OSCEN = 1 (TMR1 is

running from the LP oscillator), then the LP

oscillator will continue to run during Sleep mode.

In all oscillator modes except for INTOSC with no

CLKOUT and LP, the T1OSC enable option is unavail-

able and is ignored.

6.7

Resetting Timer1 Using a CCP

Trigger Output

If the CCP1 or CCP2 module is configured in Compare

mode

generate

“special

event

trigger”

(CCP1M<3:0> = 1011), this signal will reset Timer1.

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1 or CCP2, the write will

take precedence.

In this mode of operation, the CCPRxH:CCPRxL register

pair effectively becomes the period register for Timer1.

Note:

The ANSEL (91h) and CMCON0 (9Ch)

registers must be initialized to configure an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

Note:

When INTOSC without CLKO oscillator is

selected and T1OSCEN = 1, the LP

oscillator will run continuously independent

of the TMR1ON bit.

Note:

The special event triggers from the CCP1

and CCP2 modules will not set interrupt

flag bit, TMR1IF (PIR1<0>).

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