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PIC16F913 bảng dữ liệu(PDF) 74 Page - Microchip Technology |
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PIC16F913 bảng dữ liệu(HTML) 74 Page - Microchip Technology |
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74 / 272 page ![]() PIC16F917/916/914/913 DS41250E-page 72 Preliminary © 2005 Microchip Technology Inc. TABLE 4-1: OSCILLATOR DELAY EXAMPLES System Clock Source Frequency Switching From Oscillator Delay (TOST) Comments LFIOSC 31 kHz Sleep 10 μs internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. HFIOSC 125 kHz-8 MHz Sleep 10 μs internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. XT or HS 4-20 MHz INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an OST of 1024 cycles must occur. LP 32 kHz INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an OST of 1024 cycles must occur. See Section 4.3.1.1 “Special Case” for special case conditions. LP with T1OSC enabled 32 kHz Sleep 10 μs internal delay Following a wake-up from Sleep mode, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. See Section 4.3.1.1 “Special Case” for details about this special case. EC, RC 0-20 MHz Sleep 10 μs internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. EC, RC 0-20 MHz LFIOSC 10 μs internal delay Following a switch from a LFIOSC or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. |
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