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PIC16F913 bảng dữ liệu(PDF) 22 Page - Microchip Technology |
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PIC16F913 bảng dữ liệu(HTML) 22 Page - Microchip Technology |
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22 / 272 page  PIC16F917/916/914/913 DS41250E-page 20 Preliminary © 2005 Microchip Technology Inc. TABLE 2-4: PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1) Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 18Ch EECON1 EEPGD — — — WRERR WREN WR RD 0--- x000 0--- q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. |
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