PIC16F913 datasheet(73/272 Pages) MICROCHIP

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Preliminary

DS41250E-page 71

PIC16F917/916/914/913

4.2

Clock Source Modes

Clock source modes can be classified as external or

internal.

• External clock modes rely on external circuitry for

the clock source. Examples are oscillator modules

(EC mode), quartz crystal resonators or ceramic

resonators (LP, XT and HS modes), and

Resistor-Capacitor (RC mode) circuits.

• Internal clock sources are contained internally

within the PIC16F917/916/914/913. The

PIC16F917/916/914/913 has two internal oscilla-

tors: the 8 MHz High-Frequency Internal Oscilla-

tor (HFINTOSC) and 31 kHz Low-Frequency

Internal Oscillator (LFINTOSC).

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit (see Section 4.5 “Clock Switching”).

4.3

External Clock Modes

4.3.1

OSCILLATOR START-UP TIMER

(OST)

If the PIC16F917/916/914/913 is configured for LP, XT

or HS modes, the Oscillator Start-up Timer (OST)

counts 1024 oscillations from the OSC1 pin, following a

Power-on Reset (POR), and the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

providing

stable

system

clock

the

PIC16F917/916/914/913. When switching between

clock sources a delay is required to allow the new clock

to stabilize. These oscillator delays are shown in

Table 4-1.

4.3.1.1

Special Case

An exception to this is when the device is put to Sleep

while the following conditions are true:

• LP is the selected primary oscillator mode.

• T1OSCEN = 1 (Timer1 oscillator is enabled).

•SCS = 0 (oscillator mode is defined by

FOSC<2:0>).

• OSTS = 1 (device is running from primary system

clock).

For this case, the OST is not necessary after a wake-up

from Sleep, since Timer1 continues to run during Sleep

and uses the same LP oscillator circuit as its clock

source. For these devices, this case is typically seen

when the LCD module is running during Sleep.

In applications where the OSCTUNE register is used to

shift the FINTOSC frequency, the application should not

expect the FINTOSC frequency to stabilize immediately.

In this case, the frequency may shift gradually toward

the new value. The time for this frequency shift is less

than eight cycles of the base frequency.

Table 4-1 shows examples where the oscillator delay is

invoked.

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 4.6

“Two-Speed Clock Start-up Mode”).

Note:

When the OST is invoked, the WDOG is

held in Reset, because the WDOG ripple

counter is used by the OST to perform the

oscillator delay count. When the OST

count has expired, the WDOG will begin

counting (if enabled).

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