STM32F469 datasheet(38/91 Pages) STMICROELECTRONICS

38 / 91 page

Creating a graphical application with LTDC

AN4861

38/91

DocID029237 Rev 2

Note:

Decreasing the system clock (HCLK then LTDC) leads to a degradation of graphic

performances.

Example of supported display resolutions for STM32F4x9 line and STM32F7

Series

Table 12 lists an example of some standard and custom display sizes supported by the

STM32F4x9 line and the STM32F7 Series in the following conditions:

•

For the STM32F4x9 line the system clock HCLK is running @ 180 MHz and the

SDRAM is @ 90 MHz.

•

For the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 lines the system

clock HCLK is running @ 200 MHz and the SDRAM is @ 100 MHz.

•

Only one LTDC layer used.

•

Two AHB masters concurrent access to the SDRAM (LTDC + DMA2D).

Table 11. STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 with HCLK @ 200 MHz and

SDRAM@ 100 MHz maximal supported pixel clock versus

LTDC configuration and SDRAM bus width

Used LTDC layers

Color depth

(bpp)

Maximum pixel clock (MHz)

LTDC

LTDC + DMA2D

SDRAM 16-bit

SDRAM 32-bit

SDRAM 16-bit

SDRAM 32-bit

1 layer

8383

2 layers

32/32

2137

1220

32/24

2442

1423

32/16

2849

1728

32/8

3459

2134

24/24

2949

1727

24/16

3459

2033

24/8

4274

2642

16/16

4374

2541

16/8

5783

3456

8/8

8383

5182

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