STM32F469 datasheet(56/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

AN4861

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DocID029237 Rev 2

Based on Table 14, the extracted timing parameters are:

–

Display period (active width) = 480 pixels

–

Back porch HBP = 43 pixels

–

Front porch HFP = 8 pixels

–

Pulse width HSYNC = 1 pixel (minimum value)

–

Display period (active height) = 272 pixels

–

Vertical back porch VBP = 12 pixels

–

Front porch VFP = 4 pixels

–

Pulse width VSYNC = 10 pixel

Program timing parameters: once that the timing parameters are extracted, they are

used to program the LTDC timing registers, Table 15 summarizes all the parameters to

be programmed.

Timing parameters configuration with STM32CubeMX: it is very easy to program

the timing parameters using STM32CubeMX, the user should simply fill the extracted

parameters in the LTDC configuration window (see section Section 6.2.4: LTDC

peripheral configuration).

Pixel clock configuration with STM32CubeMX: the pixel clock is calculated with a

60 Hz refresh rate as shown below:

LCD_CLK = TOTALW x TOTALH x refresh rate

Based on Table 15, TOTALW = 531 and TOTALH = 297.

And for this example:

LCD_CLK = 531 x 297 x 60 = 9.5 MHz

Refer to the LTDC pixel clock configuration STM32CubeMX example in Section 6.2.4.

LTDC control signals polarity configuration

The LTDC control signals (HSYNC, VSYNC, DE and LCD_CLK) polarities must be

configured respecting the display specifications. The user should note that only the DE

control signal should be inverted versus the DE polarity indicated in the display datasheet.

The other control signals should be configured exactly like the display datasheet.

Table 15. Programming LTDC timing registers

Value to be

programmed

LTDC_SSCR

HSW[11:0]

HSYNC Width - 1

VSH[11:0]

VSYNC Height - 1

LTDC_BPCR

AHBP[11:0]

HSYNC Width + HBP - 1

AVBP[10:0]

VSYNC Height + VBP - 1

LTDC_AWCR

AAW[11:0]

HSYNC Width + HBP + Active Width - 1

523

AAH[10:0]

VSYNC Height + BVBP + Active Height - 1

293

LTDC_TWCR

TOTALW[11:0] HSYNC Width + HBP + Active Width + HFP - 1

531

TOTALH[10:0]

VSYNC Height+ BVBP + Active Height + VFP - 1

297

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