STM32F469 datasheet(73/91 Pages) STMICROELECTRONICS

73 / 91 page

DocID029237 Rev 2

73/91

AN4861

LTDC application examples

Pixel clock configuration

The LCD_CLK should be calculated using the parameters found in the display

datasheet.

In order to do the calculation, the user should determine the total width and the total

height.

The pixel clock is calculated with a 60 Hz refresh rate as shown below:

LCD_CLK = TOTALW x TOTALH x refresh rate (see extracted display timing

parameters in Section 4.7.2: LTDC clocks and timings configuration)

LCD_CLK = 531 x 297 x 60 = 9.5 MHz

To configure the LTDC pixel clock to 9.5 MHz using STM32CubeMX, select the clock

configuration tab then set the PLLSAI and the prescalers as shown in the Figure 45.

Figure 45. STM32CubeMX: LTDC pixel clock configuration

Timing parameters configuration

In order to configure the display timings using STM32CubeMX, the user should extract

the timing parameters from the device’s datasheet. For this example, see an extract of

ROCKTECH datasheet on Table 14. It is recommended to use the typical display

timings.

In order to configure the display timing, the user must go to the configuration tab as

indicated in Figure 38, and then click on the LTDC button.

In the LTDC configuration window, the user should select the Parameter Settings tab

and fill in the timing values (refer to Figure 46).

LTDC control signals polarity configuration

Referring to the display datasheet, the HSYNC and VSYNC should be active low and

the DE signal should be active high. As the DE signal is inverted in the output then it

should be set to active low as well. The LCD_CLK signal should not be inverted.

Figure 46 shows both the control signal polarity configuration as well the LTDC

configuration according to the ROCKTECH display datasheet.

STM32F469 bảng dữ liệu(PDF) 73 Page - STMicroelectronics