STM32F469 datasheet(22/91 Pages) STMICROELECTRONICS

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LCD-TFT (LTDC) display controller description

AN4861

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DocID029237 Rev 2

Figure 12. LTDC signal interface

The LTDC can output data according to the following parallel formats: RGB565, RGB666

and RGB888. So a 16-bit RGB565, 18-bit RGB888 or a 24-bit RGB888 display can be

connected.

LTDC signals programmable polarity

The LTDC control signals polarity is programmable allowing the STM32 microcontroller to

drive any RGB parallel display. The control signals (Hsync, Vsync and data enable DE) as

well as the pixel clock (LCD_CLK) can be defined to be active high or active low through the

LTDC_GCR register.

3.2.2

Fully programmable timings for different display sizes

Thanks to its “timings flexibility”, the LTDC peripheral can support any display size that

respects the maximal programmable timing parameters in the registers and the maximal

supported pixel clock described in Table 3, Table 11 and Table 13.

The user should consider the timings registers described in Table 6 when programming as

the LTDC timings and synchronization signals should be programmed to match the display

specification.

Table 6 summarizes the timings registers supported by the LTDC.

Table 6. LTDC timing registers

Timing parameter

Value to be

programmed

LTDC_SSCR(1)

HSW[11:0]

HSYNC width - 1

From 1 to 4096 pixels

VSH[11:0]

VSYNC height - 1

From 1 to 2048 lines

LTDC_BPCR

AHBP[11:0]

HSYNC width + HBP - 1

From 1 to 4096 pixels

AVBP[10:0]

VSYNC height + VBP - 1

From 1 to 2048 lines

LTDC_AWCR

AAW[11:0]

HSYNC width + HBP + active width - 1

From 1 to 4096 pixels

AAH[10:0]

VSYNC height + BVBP + active height - 1

From 1 to 2048 lines

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