68HC705JB3 datasheet(65/134 Pages) FREESCALE

65 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

16-BIT TIMER

MOTOROLA

REV 1

9-9

Figure 9-10. Timer Output Compare Block Diagram

To prevent OCF from being set between the time it is read and the time the output

compare registers are updated, use the following procedure:

Disable interrupts by setting the I bit in the condition code register.

Write to the OCRH. Compares are now inhibited until OCRL is written.

Read the TSR to arm the OCF for clearing.

Enable the output compare registers by writing to the OCRL. This also

clears the OCF ﬂag bit in the TSR.

Enable interrupts by clearing the I bit in the condition code register.

A software example of this procedure is shown below.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OCRH

OCRH7

OCRH6

OCRH5

OCRH4

OCRH3

OCRH2

OCRH1

OCRH0

$0016

reset:

UUUUUUUU

OCRL

OCRL7

OCRL6

OCRL5

OCRL4

OCRL3

OCRL2

OCRL1

OCRL0

$0017

reset:

UUUUUUUU

U = UNAFFECTED BY RESET

Figure 9-11. Output Compare Registers (OCRH, OCRL)

OCRH ($0016)

16-BIT COUNTER

÷ 4

INTERNAL

(fOSC ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

OUTPUT COMPARE

RESET

CLOCK

INTERRUPT

OCRL ($0017)

TIMER STATUS REG.

$0012

$0013

INTERNAL

($FFFC)

DATA

R/W

OCRH

R/W

OCRL

BUS

16-BIT COMPARATOR

(OCF)

PC0/

OCMP

MUX

OCMPO (bit7 at $06)

PORT-C LOGIC

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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