68HC705JB3 datasheet(35/134 Pages) FREESCALE

35 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

INTERRUPTS

MOTOROLA

REV 1

4-5

The IRQE enable bit controls whether an active IRQF ﬂag can generate an IRQ

interrupt sequence. This interrupt is serviced by the interrupt service routine

located at the address speciﬁed by the contents of $1FFA and $1FFB.

If IRQF is set, the only way to clear this ﬂag is by writing a logic one to the IRQR

acknowledge bit in the ICSR. As long as the output state of the IRQF ﬂag bit is

active the CPU will continuously re-enter the IRQ interrupt sequence until the

active state is removed or the IRQE enable bit is cleared.

Figure 4-3. External Interrupt (IRQ) Logic

4.5.2 IRQ Control/Status Register (ICSR) - $0A

The IRQ interrupt function is controlled by the ICSR located at $000A. All unused

bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is

set by reset.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ICSR

IRQE

IRQF

IRQPU

$000A

IRQR

reset:

10000000

Figure 4-4. IRQ Control and Status Register (ICSR)

IRQ

LATCH

VDD

RST

IRQ VECTOR FETCH

IRQ STATUS/CONTROL REGISTER

EXTERNAL

INTERRUPT

REQUEST

INTERNAL DATA BUS

TO BIH & BIL

INSTRUCTION

PROCESSING

IRQ Level

(Mask Option)

PA0

PA1

PA2

PA3

Port A External Interrupt

(Mask Option)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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