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ADV7183ABST bảng dữ liệu(PDF) 11 Page - Analog Devices |
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ADV7183ABST bảng dữ liệu(HTML) 11 Page - Analog Devices |
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11 / 104 page ![]() ADV7183A Rev. A | Page 11 of 104 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VS 1 HS 2 DGND 3 DVDDIO 4 P11 5 P10 6 P9 7 P8 8 DGND 9 DVDD 10 NC 11 SFL 12 NC 13 DGND 14 DVDDIO 15 NC 16 NC 17 NC 18 P7 19 P6 20 AIN5 60 AIN11 59 AIN4 58 AIN10 57 AGND 56 CAP C2 55 CAP C1 54 AGND 53 CML 52 REFOUT 51 AVDD 50 CAP Y2 49 CAP Y1 48 AGND 47 AIN3 46 AIN9 45 AIN2 44 AIN8 43 AIN1 42 AIN7 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ADV7183A TOP VIEW (Not to Scale) NC = NO CONNECT Figure 5. 80-Lead LQFP Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type Function 3, 9, 14, 31, 71 DGND G Digital Ground. 39, 40, 47, 53, 56 AGND G Analog Ground. 4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V). 10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V). 50 AVDD P Analog Supply Voltage (3.3 V). 38 PVDD P PLL Supply Voltage (1.8 V). 41–46, 57–62 AIN1–AIN12 I Analog Video Input Channels. 11, 13, 16–18, 25, 34, 35, 63, 65, 69, 70, 77, 78 NC No Connect Pins. 5–8, 19–24, 32, 33, 73–76 P0–P15 O Video Pixel Output Port. 2 HS O HS is a horizontal synchronization output signal. 1 VS O VS is a vertical synchronization output signal. 80 FIELD O FIELD is a field synchronization output signal. 67 SDA I/O I2C Port Serial Data Input/Output Pin. 68 SCLK I I2C Port Serial Clock Input (Max Clock Rate of 400 kHz). 66 ALSB I This pin selects the I2C address for the ADV7183A. ALSB set to Logic 0 sets the address for a write as 0x40; for ALSB set to logic high, the address selected is 0x42. 64 RESET I System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7183A circuitry. 27 LLC1 O This is a line-locked output clock for the pixel data output by the ADV7183A. Nominally 27 MHz, but varies up or down according to video line length. 26 LLC2 O This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7183A. Nominally 13.5 MHz, but varies up or down according to video line length. |
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