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ADV7183ABST bảng dữ liệu(PDF) 96 Page - Analog Devices

tên linh kiện ADV7183ABST
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ADV7183ABST bảng dữ liệu(HTML) 96 Page - Analog Devices

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ADV7183A
Rev. A | Page 96 of 104
Table 207. Registers 0xE8 to 0xEA
Bit
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
PVBEG[4:0]. How many lines after lCOUNT rollover
to set V high.
0
0
1
0
1
PAL Default (BT.656)
0
Set to low when manual
programming
PVBEGSIGN
1
Not suitable for user
programming
0
No delay
PVBEGDELE. Delay V bit going high by one line
relative to PVBEG (even field).
1
Additional delay by 1 line
0
No delay
0xE8
PAL V Bit
Begin
PVBEGDELO. Delay V bit going high by one line
relative to PVBEG (odd field).
1
Additional delay by 1 line
PVEND[4:0]. How many lines after lCOUNT rollover
to set V low.
1
0
1
0
0
PAL Default (BT.656)
0
Set to low when manual
programming
PVENDSIGN
1
Not suitable for user
programming
0
No delay
PVENDDELE. Delay V bit going low by one line
relative to PVEND (even field).
1
Additional delay by 1 line
0
No delay
0xE9
PAL V Bit
End
PVENDDELO. Delay V bit going low by one line
relative to PVEND (odd field).
1
Additional delay by 1 line
PFTOG[4:0]. How many lines after lCOUNT rollover
to toggle F signal.
0
0
0
1
1
PAL Default (BT.656)
0
Set to low when manual
programming
PFTOGSIGN.
1
Not suitable for user
programming
0
No delay
PFTOGDELE. Delay F transition by one line
relative to PFTOG (even field).
1
Additional delay by 1 line
0
No delay
0xEA
PAL F Bit
Toggle
PFTOGDELO. Delay F transition by one line
relative to PFTOG (odd field).
1
Additional delay by 1 line



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