ADV7183ABST datasheet(75/104 Pages) AD

75 / 104 page

ADV7183A

Rev. A | Page 75 of 104

Table 180. Register 0x09 to 0x0E

Bit

Subaddress

Bit Description

Comments

0x09

Reserved

(Saturation)

Reserved

0x0A

Brightness

BRI[7:0]. This register controls

the brightness of the video

signal.

0x00 = 0IRE;

0x7F = 100IRE;

0xFF = –100IRE

0x0B

Hue Register

HUE[7:0]. This register

contains the value for the color

hue adjustment.

Hue range =

–90° to +90°

0x0C

Default Value Y

Free Run mode

dependent on

DEF_VAL_AUTO_EN

DEF_VAL_EN. Default value

enable.

Force SDP Free Run

mode on and output

blue screen

Disable SDP Free Run

mode

DEF_VAL_AUTO_EN. Default

value.

Enable Automatic Free

Run mode (blue

screen)

When lock is lost,

Free Run mode

can be enabled

to output stable

timing, clock,

and a set color.

DEF_Y[5:0]. Default value Y.

This register holds the Y

default value.

Y[7:0] = {DEF_Y[5:0],

0, 0, 0, 0}

Default Y value

output in free-

run mode.

0x0D

Default Value C

Cr[7:0] = {DEF_C[7:4],

0, 0, 0, 0, 0, 0}

Cb[7:0] = {DEF_C[3:0],

0, 0, 0, 0, 0, 0}

DEF_C[7:0]. Default value C. Cr

and Cb default values are

defined in this register.

Default Cb/Cr

value output in

Free Run mode.

Default values

give blue screen

output.

0x0E

ADI Control

Low drive strength

(1×)

Medium-low (2×)

Medium-high (3×)

DR_STR_S[1:0]. Select the

drive strength of the sync

signals. HS, VS, and F can be

increased or decreased for

EMC or crosstalk reasons.

High drive strength

(4×)

Low drive strength

(1×)

Medium-low (2×)

Medium-high (3×)

DR_STR_C[1:0]. Select the

strength of the clock signal

output driver. Can be

increased or decreased for

EMC or crosstalk reasons.

High drive strength

(4×)

Reserved

Set as default

LLC pin active

TRI_LLC. Enables the LLC pin

to be three-stated.

LLC pin drivers three-

stated

See TOD

(

Table 177);

TIM_OE

(

Table 178).

Reserved

Set as default

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