DSP56857 datasheet(137/662 Pages) FREESCALE

137 / 662 page

External Memory Interface (EMI), Rev. 4

Freescale Semiconductor

5-11

5.6.3.3 Read Wait States Setup Delay (RWSS)—Bits 11–10

This field affects the read cycle timing diagram, illustrated in Figure 5-10. Additional time

(clock cycles) is provided between the assertion of CSn and address lines and the assertion of

RD. The value of RWSS should be set as indicated in Read Timing.

5.6.3.4 Read Wait States Hold Delay (RWSH)—Bits 9–8

This field affects the read cycle timing diagram, illustrated in Figure 5-11. The RWSH field

specifies the number of additional system clocks to hold the address, data, and CSn signals after

the RD signal is deasserted. The value of RWSH should be set as indicated in Section 5.7.1.

Note:

If both, the RWSS and RWSH fields are set to zero the EMI read timing is set for

consecutive mode. In this mode the RD signal will remain active during back-to-back

reads from the same CSn controlled memory space.

5.6.3.5 Reserved—Bits 7–3

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.3.6 Minimal Delay After Read (MDAR)—Bits 2–0

This field specifies the number of system clocks to delay between reading from memory in a CSn

controlled space and reading from another device. Since a write to the device implies activating

the digital signal controller on the bus, this is also considered a read from another device.

Figure 5-6 illustrates the timing issue requiring the introduction of the MDAR field. In this

diagram, CS1 is assumed to operate a slow flash memory in P-space while CS2 is operating a

faster RAM in X-space. In some bus contention cases, it is possible to encounter data integrity

problems where the contention is occurring at the time the data bus is sampled.

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