DSP56857 datasheet(139/662 Pages) FREESCALE

139 / 662 page

External Memory Interface (EMI), Rev. 4

Freescale Semiconductor

5-13

5.6.4.2 Base Minimal Delay After Read (BMDAR)—Bits 14–12

This bit field specifies the number of system clocks to delay after reading from memory not in CS

controlled space. Since a write to the device implies activating the digital signal controller on the

bus, this is also considered a read from another device, therefore activating the BMDAR timing

control. Please see the description of the MDAR field of the CSTC registers for a discussion of

the function of this control.

5.6.4.3 Reserved—Bits 11–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.4.4 Base Write Wait States (BWWS)—Bits 9–5

This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for

write access to the selected memory when the memory address does not fall within CS controlled

range. The value of BWWS should be set as indicated in Timing Specifications.

5.6.4.5 Base Read Wait States (BRWS)—Bits 4–0

This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for

read access to the selected memory when the memory address does not fall within CS controlled

range. The value of BRWS should be set as indicated in Section 5.7.

Table 5-6. Operation with DRV

800E Core Operating State

DRV

Pins

A23:A0

RD, WR, CSn

D15:D0

EMI is Between External Memory Accesses

Tri-stated

Reset Mode

Tri-stated

Pulled High Internally

Tri-stated

EMI is Between External Memory Accesses

Driven

Driven (RD, WR, CSn are Deasserted)

Tri-stated

Reset Mode

Tri-stated

Pulled High Internally

Tri-stated

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