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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DSP56857 bảng dữ liệu(PDF) 133 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 133 Page - Freescale Semiconductor, Inc |
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133 / 662 page  Register Descriptions (EMI_BASE = $1FFE40) External Memory Interface (EMI), Rev. 4 Freescale Semiconductor 5-7 Figure 5-2. EMI Register Map Summary 5.6 Register Descriptions (EMI_BASE = $1FFE40) 5.6.1 Chip Select Base Address Registers 0–3 (CSBAR0–CSBAR3) The CSBAR registers are defined in Figure 5-3. It determines the active address range of a given CSn. The Block Size (BLKSZ) field determines the size of the memory map covered by the CSn. This field also determines which of the address bits to use when specifying the base address of the CSn. This encoding is detailed in Table 5-2. When the active bits match the address and the constraints specified in the CSOR are also met, the CSn is asserted. The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be an integer multiple of the block size (i.e., Add. Offset Register Name 15 14 13 12 11 10 98765432 1 0 $0 CSBAR0 R ADR 23 ADR 22 ADR 21 ADR 20 ADR 19 ADR 18 ADR 17 ADR 16 ADR 15 ADR 14 ADR 13 ADR 12 BLKSZ W $1 CSBAR1 R ADR 23 ADR 22 ADR 21 ADR 20 ADR 19 ADR 18 ADR 17 ADR 16 ADR 15 ADR 14 ADR 13 ADR 12 BLKSZ W $2 CSBAR2 R ADR 23 ADR 22 ADR 21 ADR 20 ADR 19 ADR 18 ADR 17 ADR 16 ADR 15 ADR 14 ADR 13 ADR 12 BLKSZ W $3 CSBAR3 R ADR 23 ADR 22 ADR 21 ADR 20 ADR 19 ADR 18 ADR 17 ADR 16 ADR 15 ADR 14 ADR 13 ADR 12 BLKSZ W $8 CSOR0 R RWS BYTE_EN R/W PS/DS WWS W $9 CSOR1 R RWS BYTE_EN R/W PS/DS WWS W $A CSOR2 R RWS BYTE_EN R/W PS/DS WWS W $B CSOR3 R RWS BYTE_EN R/W PS/DS WWS W $10 CSTC0 R WWSS WWSH RWSS RWSH 0 0 0 0 0 MDAR W $11 CSTC1 R WWSS WWSH RWSS RWSH 0 0 0 0 0 MDAR W $12 CSTC2 R WWSS WWSH RWSS RWSH 0 0 0 0 0 MDAR W $13 CSTC3 R WWSS WWSH RWSS RWSH 0 0 0 0 0 MDAR W $18 BCR R DRV BMDAR 0 0 BWWS BRWS W R 0 Read as 0 W Reserved |
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