DSP56857 datasheet(129/662 Pages) FREESCALE

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Features

External Memory Interface (EMI), Rev. 4

Freescale Semiconductor

5-3

5.1 Introduction

The External Memory Interface (EMI) provides an interface allowing 56800E core to utilize

external asynchronous memory. The EMI for the 56800E core operates from the system bus.

The 56800E core EMI is implemented as a core bus peripheral. Data can be transferred through

the EMI to the core directly.

The EMI described in this document is intended to be interfaced to 16-bit wide external memory.

External arrays may be implemented either using single 16-bit wide parts or pairs of 8-bit wide

memories. An external data space memory interface to the 56800E core accommodating single

8-bit wide external data memories could be implemented (at a substantial performance penalty)

with appropriate programming of the CSOR register(s).

5.2 Features

The External Memory Interface supports the following general characteristics:

•

Can convert any internal bus memory request to a request for external memory

•

Can manage multiple internal bus requests for external memory access

•

Has up to four CSn configurable outputs for external device decoding

— each CS can be configured for Program or Data space

— each CS can be configured for Read only, Write only, or Read/Write access

— each CS can be configured for the number of wait states required for device access

— each CS can be configured for the size and location of its activation

— each CS is independently configured for setup and hold timing controls for both read

and write

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