DSP56857 datasheet(126/662 Pages) FREESCALE

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Resets

5685X Digital Signal Controller User Manual, Rev. 4

4-18

Freescale Semiconductor

The SIM generates four reset outputs. All are active low. These all are activated by one of the two

detectors but remain asserted for 32-system clock cycles after the detector deasserts. This permits

the SIM to generate 32-system clock cycles of continuous clocking to the part while the reset

remains asserted. This is required to clear synchronous resets within the 56800E core and

elsewhere in the part. The RST_CORE, RST_PERIPH, and RST_CGM outputs are activated by

the chip-internal reset detector and the RST_TOD output is activated by the POR reset detector.

The RST_CORE output is used to reset the core. The RST_TOD output is used to reset all

controls used to configure time-of-day clock to retain their value once the part is powered on. See

TOD, COP, OSC chapters. The RST_CGM is re-timed to the OSC_CLK and is used to reset the

CGM module, in turn using the oscillator clock directly. The RST_PERIPH reset is used to reset

everything else.

Standards require the part to be held in reset during boundary scan operations. When the

BSCAN_EBL input is asserted, all resets used within the SIM and all reset outputs of the SIM

will go to their active asserted state. This prevents accidental damage due to random inputs

applied during boundary scan testing.

Power modes discussed in Section 4.9 affect reset function. COP reset is not honored if the OSC

module is in its Low Power mode since the OSC module shuts off all clocking to the part and

without a clock, the SIM can’t see the synchronous COP reset. COP reset will be honored

immediately upon return to Run mode when clocks resume. There are two ways to permit a COP

reset to be honored in Stop mode:

1. Either set OMR6_SD (core register OMR6 bit SD), or

2. Set TOD_SEL in the CGM control register

Setting OMR6_SD configures for fast Stop mode recovery. Setting TOD_SEL selects the CGM’s

time-of-day clock prescaler for use rather than the one in the OSC module. Either, or both,

prevent the OSC from shutting off its clock outputs. In turn, this provides an active CLK_MSTR

input to the SIM, allowing an immediate COP reset. The Software Reset is only operable in Run

mode when the CPU can write to the SIM Control register to activate Software Reset.

The Low

Power modes and controls are explained in detail in the next chapter.

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