DSP56857 datasheet(596/662 Pages) FREESCALE

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Sheet

56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4

B-94

Freescale Semiconductor

Preliminary

11 of 11

TMR Status/Control Register (SCR) continued

TMR

TMR Status/Control

$1FFE80 + $7, $F,

$17, $1F

Bits

Read

TCF TCFIE TOF TOFOE IEF IEFIE IPS

INPUT

CAPTURE

MODE

MSTR EEOF VAL

OPS OEN

Write

FORCE

Reset

denotes Reserved Bits

Bits

Name

Description

7 - 6

CAPTURE MODE

Input Capture Mode

These bits specify the operation of the Capture register and the operation of the input edge flag.

Capture function is disabled

Load Capture register on rising edge of input

Load Capture register on falling edge of input

Load Capture register on any edge of input

MSTR

Master Mode

When set, this bit enables Compare function’s output to be broadcasted to the other

counter/timers in the module. This signal can then be used to reinitialize the other counters and/or

force their OFLAG signal outputs.

EEOF

Enable External OFLAG Force

When set, this bit enables the Compare from another counter/timer within the same module to

force the state of this counter’s OFLAG output signal.

VAL

Forced OFLAG Value

This bit determines the value of the OFLAG output signal when a software triggered FORCE

command, or another counter/timer set as a master, issues a FORCE command.

FORCE

Force OFLAG Output

This write-only bit forces the current value of the VAL bit to be written to the OFLAG output. This

bit is read as 0. The VAL and FORCE bits can be written simultaneously in a single write

operation. Write to the FORCE bit only when the counter is disabled.

No action

Forces the current value of the Val bit to be written to OFLAG output

OPS

Output Polarity Select

This bit determines the polarity of the OFLAG output signal.

True polarity

Inverted polarity

OEN

Output Enable

When set, this bit enables the OFLAG output signal to be placed on the external pin. Setting this

bit connects a timer’s output pin to its input. Polarity of the signal will be determined by OPS bit.

TMRA0_SCR (Timer A, Channel 0 Status/Control)—Address: TMRA_BASE + $7

TMRA1_SCR (Timer A, Channel 1 Status/Control)—Address: TMRA_BASE + $F

TMRA2_SCR (Timer A, Channel 2 Status/Control)—Address: TMRA_BASE + $17

TMRA3_SCR (Timer A, Channel 3 Status/Control)—Address: TMRA_BASE + $1F

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