DSP56857 datasheet(592/662 Pages) FREESCALE

592 / 662 page

Application:

Date:

Programmer:

Sheet

56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4

B-90

Freescale Semiconductor

Preliminary

7 of 11

TMR

TMR Control Register (CTL)

Bits

Name

Description

15 - 13

Count Mode

These bits control the basic counting behavior of the counter

000

No operation

001

Count rising edges of primary source.

010

Count rising and falling edges of primary source.

011

Count rising edges of primary source while secondary input is active high

100

Quadrature Count mode uses primary and secondary sources

101

Count primary source rising edges, secondary source specifies direction (1=minus)

110

Edge of secondary source triggers primary count until compared

111

Cascaded Counter mode (up/down)

12 - 9

PCS

Primary Count Service Source

These bits select the primary count source

0000

Counter 0 input pin (TIO0)

0001

Counter 1 input pin (TIO1)

0010

Counter 2 input pin (TIO2)

0011

Counter 3 input pin (TIO3)

0100

Counter 0 output (OFLAG0)

0101

Counter 1 output (OFLAG1)

0110

Counter 2 output (OFLAG2)

0111

Counter 3 output (OFLAG3)

1000

Prescaler (IPBus clock divide by 1)

1001

Prescaler (IPBus clock divide by 2)

1010

Prescaler (IPBus clock divide by 4)

1011

Prescaler (IPBus clock divide by 8)

1100

Prescaler (IPBus clock divide by 16)

1101

Prescaler (IPBus clock divide by 32)

1110

Prescaler (IPBus clock divide by 64)

1111

Prescaler (IPBus clock divide by 128)

TMR Control

$1FFE80 + $6, $E,

$16, $1E

Bits

Read

PCS

SCS

ONCE LENGTH DIR

EXT

INIT

OM (OFLAG)

Write

Reset

0000

00000

See the following page for continuation of this register

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