DSP56857 datasheet(580/662 Pages) FREESCALE

580 / 662 page

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Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-78

Preliminary

11 of 16

ESSI Transmit and Receive Control Registers (STXCR, SRXCR)

Bits

Name

Description

PSR

Prescaler Range

This bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends

the range of the prescaler for those cases where a slower bit clock is desired.

When the PSR bit is cleared, the fixed prescaler is by-passed

When the PSR bit is set, the fixed divide-by eight prescaler is operational

14 - 13

Word Length Control

These bits are used to select the length of the data words being transferred by the ESSI

12 - 8

Frame Rate Divider Control

This bit field controls the divide ratio for the programmable frame rate dividers

7 - 0

Prescaler Modulus Select

This bit field specifies the divide ratio of the prescale divider in the ESSI clock generator. This

prescaler is used only in internal clock mode to divide the internal peripheral clock.

ESSI

ESSI Transmit

Control Register

(STXCR)

Base + $8

Bits

Read

PSR

Write

Reset

000

ESSI Receive

Control Register

(SRXCR)

Base + $9

Bits

Read

PSR

Write

Reset

000

0000

000

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