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DSP56857 bảng dữ liệu(PDF) 577 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 577 Page - Freescale Semiconductor, Inc |
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577 / 662 page ![]() Application: Date: Programmer: Sheet C 56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4 B-75 Freescale Semiconductor Preliminary Bits Name Description 2 SYNRST Frame Sync Reset 0 Data must be read to be cleared from the registers 1 Resets the accumulation of data in the SRX register and RXFIFO bit in frame sync 1 RLIE Receive Last Slot Interrupt Enable 0 The Receive Last Slot Interrupt is disabled 1 An interrupt is generated after the last slot of a receive frame ends when the ESSI is in the Network mode. Interrupt occurs regardless of the receive mask register setting. 0 TLIE Transmit Last Slot Interrupt Enable 0 The Transmit Last Slot Interrupt is disabled 1 An interrupt is generated at the beginning of the last slot of the transmit frame when the ESSI is in the Network mode. The interrupt occurs regardless of the transmit mask register setting. 8 of 16 ESSI Control Register 3 (SCR3) continued ESSI denotes Reserved Bits ESSI Control Register 3 (SCR3) Base + $6 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DIV4DIS RSHFD RSCKP RDMAE TDMAE RFSI RFSL REFS RFEN TFEN INIT SYN RST RLIE TLIE Write Reset 0 0 0 0 0 0 0 0 0 0 00 00 0 0 |
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