DSP56857 datasheet(556/662 Pages) FREESCALE

556 / 662 page

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Date:

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Sheet

5685X Digital Signal Controller User Manual, Rev. 4

B-54

Freescale Semiconductor

2 of 9

SCI

SCI Control Register (SCICR)

SCI Control

Base + $1

Bits

Read

LOOP SWAI RSRC

WAKE POL

TEIE

TIIE

RFIE REIE

RWU SBK

Write

Reset

Bits

Name

Description

LOOP

Loop Select

This bit enables loop operation. Loop operation disconnects the RXD pin from the SCI and the

transmitter output goes into the receiver input. Both transmitter and receiver must be enabled to

use the internal loop function as opposed to single wire operation, requiring only one or the other

to be enabled.

Normal operation enabled

Loop operation enabled

SWAI

Stop in Wait Mode

This bit disables the SCI in the Wait mode.

SCI enabled in Wait mode

SCI disabled in Wait mode

RSRC

Receiver Source

When LOOP = 1, the RSRC bit determines the internal feedback path for the receiver.

Receiver input internally connected to transmitter output

Receiver input connected to TXD pin

Data Format Mode

The Mode bit determines whether data characters are eight or nine bits long.

One start bit, eight data bits, one stop bit

One start bit, nine data bits, one stop bit

WAKE

Wake up Condition

This bit determines which condition wakes up the SCI.

Idle line wake up

Address mark wake up

POL

Polarity

This bit determines whether to invert the data as it goes from the transmitter to the TXD pin and

from the RXD pin to the receiver. All bits (Start, Data, and Stop) will be inverted as they leave the

transmit shift register and before they enter the receive shift register.

Doesn’t invert transmit and receive data bits (Normal mode)

Invert transmit and receive data bits (Inverted mode)

See the following page for continuation of this register

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